By Robert B. Garner (auth.), Ben J. Catanzaro (eds.)
With the SPARC (Scalable Processor structure) structure and procedure software program because the underlying origin, solar Microsys terns is offering a brand new version of computing-easy workgroup computing-to improve the best way humans paintings, automating approaches throughout teams, departments, and groups in the neighborhood and globally. solar and a wide and transforming into variety of businesses within the machine have launched into a brand new method of meet the desires of machine clients and approach builders within the Nineties. Originated by way of sunlight, the strategy pursuits clients who want a diversity of appropriate desktops with numerous software tender ware and wish the choice to shop for these structures from a decision of proprietors. The method additionally meets the wishes of process builders to join a extensive, becoming marketplace of suitable structures and software-developers who have to layout items quick and cost-effecti vel y. The SPARe strategy guarantees that desktops could be effortless to take advantage of for all sessions of clients and contributors of the workgroup, finish clients, method directors, and software program builders. For the top person, the SPARC applied sciences facilitate procedure set-up and the day-by-day use of assorted functions. For the procedure administrator helping the pc set up, constructing and tracking the community are more straightforward. For the software program developer, there are advert vanced improvement instruments and aid. in addition, the good points of the SPARC and software program applied sciences make sure that SPARC platforms and purposes play an incredible function within the years to come.
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Extra resources for The SPARC Technical Papers
Brown, D. N. Joy, S. Kleiman, S. Muchnick, M. Namjoo, D. Patterson, J. G. Tan, & R. Tuck, "The Scalable Processor Architecture (SPARC)," 33rd Annual IEEE Computer Conference (COMPCON '88), March 1-3, San Francisco, CA. [Katevenis83] M. D. , Univ. of California, Berkeley, 1983. T. Press, Cambridge, MA, 1985. [KleimanC88] S. Kleiman & D. Williams, "SunOS on SPARC," 33rd Annual IEEE Computer Conference (COMPCON '88), March 1-3, San Francisco, CA. [Mahon86] M. B. C. C. Huck, & WR. , vol. 37, no. 8, Aug.
Peshkess, C. Sequin, R. Sherburne, & K. Van Dyke, "VLSI Implementations of a Reduced Instruction Set Computer," Proceedings of the CMU Conference on VLSI Systems and Computations, October, 1981, Pittsburgh, Pennsylvania. C. Chow & J. Hennessy, "Register Allocation by Priority-based Coloring," Proceedings of the SIGPLAN '86 Symposium on Compiler Construction, Montreal, Canada, June, 1984. [Dubois88] M. Dubois, C. Scheurich, & F. ,March 1988. B. Garner, A. Agrawal, F. W. Brown, D. N. Joy, S. Kleiman, S.
Floating-Point Registers The FPV has thirty-two 32-bit-wide registers. Doubleprecision values occupy an even-odd pair and extended-precision values occupy an aligned group of four registers. The FPV's registers are accessed externally only via load and store instructions; there is no direct path between the IV and the FPV. The instruc2 The cost of saving or restoring a window is not large: on the Sun-4/200, it approximates the overhead of 7 cache misses. CHAPTER 2 The Scalable Processor Architecture (SPARe) 37 tion set defines doubleword (64-bit) floating-point loads and stores to boost double-precision performance.
The SPARC Technical Papers by Robert B. Garner (auth.), Ben J. Catanzaro (eds.)